1. Field of the Invention
The present invention relates to a semiconductor storage device, e.g., a dynamic random access memory (which will be referred to as a “DRAM” hereinafter) accommodated in a system in package (which will be referred to as an “SiP” hereinafter). For example, the present invention relates to a layout structure of data input/output pads associated with a plurality of bits, power supply pads, input/output control circuits which control over, e.g., writing/reading data, and others.
2. Description of the Related Art
Prior art examples including a layout of a semiconductor storage devices having data pads associated with a plurality of bits are shown in Japanese Patent Application Laid-open No. 202145-1995 and Japanese Patent Application Laid-open No. 316436-1996.
Japanese Patent Application Laid-open No. 202145-1995 discloses a semiconductor integrated circuit device in which an output block is arranged between a bonding pad on an outer peripheral side and an external region to eliminate an excess region and a chip size is thereby reduced. Further, Japanese Patent Application Laid-open No. 316436-1996 discloses a semiconductor storage device in which sources of two N channel MOS transistors (which will be referred to as “NMOSs” hereinafter) adjacent to each other are connected in common and an area occupied the NMOSs on a chip is reduced to decrease a chip size.
FIG. 2 is a schematic layout chart showing an example of a conventional semiconductor storage device disclosed, for example, in Japanese Patent Application Laid-open No. 202145-1995 and Japanese Patent Application Laid-open No. 316436-1996. The semiconductor storage device has a chip-like shape and includes a substantially square substrate 10. A memory array section 11 which stores data is arranged on the substrate 10 near one side of an outer periphery. This memory array section 11 is constituted of a plurality of memory cells, and entirely has a substantially square shape having a lateral width of L1 and a vertical width of L2. A plurality of data pads 12 (=12-1 to 12-n) which input/output data are arranged near one side facing the memory array section 11 in parallel with this side.
Each of the plurality of data pads 12 has a substantially square shape and is connected with a non-illustrated external circuit which controls a semiconductor storage device through a data wire 15. Furthermore, the plurality of data pads 12 are connected with a plurality of input/output control circuits 13 (=13-1 to 13-n) arranged on an inner side of the plurality of data pads 12 via signal wiring lines 16 through which data is transmitted in parallel with the plurality of data pads 12.
The plurality of input/output control circuits 13 are circuits which control input data, write the data in the memory array section 11 via signal wiring lines 17, and control and output the read data from the memory array section 11 through the signal wiring lines 17, and have complementary MOS transistors (which will be referred to as “CMOSs” hereinafter) constituted of non-illustrated output NMOSs and P channel MOS transistors (which will be referred to as “PMOSs” hereinafter). The plurality of input/output control circuits 13 are connected with the memory array section 11 through the signal wiring liens 17, and also connected with power supply pads 14-1 and 14-2 via power supply wiring lines 18 through which power is supplied.
Each of the power supply pads 14-1 and 14-2 is a terminal which receives power from an external power supply, has a substantially square shape, and is arranged alone one side near the plurality of data pads 12. Moreover, the power supply pads 14-1 and 14-2 are connected with power supply voltage terminals VDD and VSS of a non-illustrated external power supply through power supply wires 19.
An operation of the semiconductor storage device depicted in FIG. 2 will now be explained. Data is input to the plurality of input/output control circuits 13 from the non-illustrated external circuit which controls the semiconductor storage device through the plurality of data pads 12. The input data is controlled by the input/output control circuits 13 to be written in the memory array section 14. The written data is read out by the input/output control circuits 13. The read data is outputted to a non-illustrated external circuit, e.g., a CPU through the data pads 12.
However, the semiconductor storage device shown in FIG. 2 has the following disadvantage. A layout side of the memory array section 11 can be reduced based on miniaturization in a semiconductor manufacturing process. However, in regard to the data pads 12 to be wire-bonded, a pad pitch which indicates a distance between the data pads 12-1 and 12-2 cannot be reduced because of a mechanical limitation of a wire bonding device.
In order to solve this problem, the technology disclosed in Japanese Patent Application Laid-open No. 202145-1995, for example, provides a structure where the plurality of data pads 12 are constituted on two stages on an outer peripheral side and an inner peripheral side to reduce a lateral width of a pad forming region 12S is considered. However, when the data pads 12 are constituted on the two stages, a vertical width of the pad forming region 12S is doubled, and a chip size is increased. In order to reduce the chip size, a decreased distance between the data pads 12 and the input/output control circuits 13 can be considered.
However, although the distance between the data pads 12 on the outer peripheral side and the input/output control circuits 13 can be reduced by utilizing an excess region, the distance between the data pads 12 on the inner peripheral side and the input/output control circuits 13 is hard to reduce since the excess region is not present. Additionally, when the distance between the data pads 12 and the input/output control circuits 13 is small, there is a problem that electrical characteristics of the input/output control circuits 13 are degraded due to noise from the data pads 12. Therefore, there exists a need to address the above-explained difficulties in the art.